mohamed sabt
2014-05-09 14:23:52 UTC
Hello,
I'm reading the article "An Exploration of ARM TrustZone Technology" and a
question was raised into my head when I reached the subsection "TZPC and
TZASC". It is mentioned that by experimenting with the Versatile Express
platform some insights were discovered. Namely, TZASC secures physical
addresses via SMC (Static Memory Controller), while TZPC secures physical
addresses via DMC (Dynamic MC). In summary, TZASC secures on-chip RAM,
namely SRAM; and TZPC secures off-chip RAM, namely DRAM.
I don't know if you're familiar with ARM TrustZone documentation, but in
this white paper of ARM
http://infocenter.arm.com/help/topic/com.arm.doc.prd29-genc-009492c/PRD29-GENC-009492C_trustzone_security_whitepaper.pdf,
it is mentioned in the sections 4.1.4 and 4.1.7 the opposite of what was
mentioned by your article.
I look forward to your answer about this. I am studying the TrustZone
architecture and reading this has just bugged me. I don't if I miss
something here.
Thank you in advance,
Mohamed Sabt
I'm reading the article "An Exploration of ARM TrustZone Technology" and a
question was raised into my head when I reached the subsection "TZPC and
TZASC". It is mentioned that by experimenting with the Versatile Express
platform some insights were discovered. Namely, TZASC secures physical
addresses via SMC (Static Memory Controller), while TZPC secures physical
addresses via DMC (Dynamic MC). In summary, TZASC secures on-chip RAM,
namely SRAM; and TZPC secures off-chip RAM, namely DRAM.
I don't know if you're familiar with ARM TrustZone documentation, but in
this white paper of ARM
http://infocenter.arm.com/help/topic/com.arm.doc.prd29-genc-009492c/PRD29-GENC-009492C_trustzone_security_whitepaper.pdf,
it is mentioned in the sections 4.1.4 and 4.1.7 the opposite of what was
mentioned by your article.
I look forward to your answer about this. I am studying the TrustZone
architecture and reading this has just bugged me. I don't if I miss
something here.
Thank you in advance,
Mohamed Sabt